FLASH

External Flash Memory. More...

Detailed Description

External Flash Memory.

IS25LP08D Commands

Macros
#define	ENTER_DEEP_POWER_DOWN   0XB9
#define	EXIT_DEEP_POWER_DOWN   0XB9
#define	RESET_ENABLE_CMD   0x66
#define	RESET_MEMORY_CMD   0x99
#define	READ_ID_CMD   0xAB
#define	READ_ID_CMD2   0x9F
#define	MULTIPLE_IO_READ_ID_CMD   0xAF
#define	READ_SERIAL_FLASH_DISCO_PARAM_CMD   0x5A
#define	READ_MANUFACT_AND_ID   0x90
#define	READ_UNIQUE_ID   0x4B
#define	NO_OP   0x00
#define	SECTOR_UNLOCK   0x26
#define	SECTOR_LOCK   0x24
#define	INFO_ROW_ERASE_CMD   0x64
#define	INFO_ROW_PROGRAM_CMD   0x62
#define	INFO_ROW_READ_CMD   0x68
#define	READ_CMD   0x03
#define	FAST_READ_CMD   0x0B
#define	FAST_READ_DTR_CMD   0x0D
#define	DUAL_OUT_FAST_READ_CMD   0x3B
#define	DUAL_INOUT_FAST_READ_CMD   0xBB
#define	DUAL_INOUT_FAST_READ_DTR_CMD   0xBD
#define	QUAD_OUT_FAST_READ_CMD   0x6B
#define	QUAD_INOUT_FAST_READ_CMD   0xEB
#define	QUAD_INOUT_FAST_READ_DTR_CMD   0xED
#define	WRITE_ENABLE_CMD   0x06
#define	WRITE_DISABLE_CMD   0x04
#define	READ_STATUS_REG_CMD   0x05
#define	WRITE_STATUS_REG_CMD   0x01
#define	READ_FUNCTION_REGISTER   0X48
#define	WRITE_FUNCTION_REGISTER   0x42
#define	WRITE_READ_PARAM_REG_CMD   0xC0
#define	PAGE_PROG_CMD   0x02
#define	QUAD_IN_PAGE_PROG_CMD   0x32
#define	EXT_QUAD_IN_PAGE_PROG_CMD   0x38
#define	SECTOR_ERASE_CMD   0xd7
#define	SECTOR_ERASE_QPI_CMD   0x20
#define	BLOCK_ERASE_CMD   0xD8
#define	BLOCK_ERASE_32K_CMD   0x52
#define	CHIP_ERASE_CMD   0xC7
#define	EXT_CHIP_ERASE_CMD   0x60
#define	PROG_ERASE_RESUME_CMD   0x7A
#define	EXT_PROG_ERASE_RESUME_CMD   0x30
#define	PROG_ERASE_SUSPEND_CMD   0x75
#define	EXT_PROG_ERASE_SUSPEND_CMD   0xB0
#define	ENTER_QUAD_CMD   0x35
#define	EXIT_QUAD_CMD   0xF5
#define	IS25LP064A_SR_WIP   ((uint8_t)0x01)
	IS25LP08D Registers
#define	IS25LP064A_SR_WREN   ((uint8_t)0x02)
#define	IS25LP064A_SR_SRWREN    ((uint8_t)0x80)
#define	IS25LP064A_SR_QE   ((uint8_t)0x40)
#define	IS25LP064A_NVCR_NBADDR    ((uint16_t)0x0001)
#define	IS25LP064A_NVCR_SEGMENT    ((uint16_t)0x0002)
#define	IS25LP064A_NVCR_DUAL   ((uint16_t)0x0004)
#define	IS25LP064A_NVCR_QUAB   ((uint16_t)0x0008)
#define	IS25LP064A_NVCR_RH   ((uint16_t)0x0010)
#define	IS25LP064A_NVCR_DTRP    ((uint16_t)0x0020)
#define	IS25LP064A_NVCR_ODS   ((uint16_t)0x01C0)
#define	IS25LP064A_NVCR_XIP    ((uint16_t)0x0E00)
#define	IS25LP064A_NVCR_NB_DUMMY    ((uint16_t)0xF000)
#define	IS25LP064A_VCR_WRAP   ((uint8_t)0x03)
#define	IS25LP064A_VCR_XIP   ((uint8_t)0x08)
#define	IS25LP064A_VCR_NB_DUMMY    ((uint8_t)0xF0)
#define	IS25LP064A_EAR_HIGHEST_SE    ((uint8_t)0x03)
#define	IS25LP064A_EAR_THIRD_SEG    ((uint8_t)0x02)
#define	IS25LP064A_EAR_SECOND_SEG    ((uint8_t)0x01)
#define	IS25LP064A_EAR_LOWEST_SEG    ((uint8_t)0x00)
#define	IS25LP064A_EVCR_ODS   ((uint8_t)0x07)
#define	IS25LP064A_EVCR_RH   ((uint8_t)0x10)
#define	IS25LP064A_EVCR_DTRP    ((uint8_t)0x20)
#define	IS25LP064A_EVCR_DUAL   ((uint8_t)0x40)
#define	IS25LP064A_EVCR_QUAD   ((uint8_t)0x80)
#define	IS25LP064A_FSR_NBADDR    ((uint8_t)0x01)
#define	IS25LP064A_FSR_PRERR   ((uint8_t)0x02)
#define	IS25LP064A_FSR_PGSUS   ((uint8_t)0x04)
#define	IS25LP064A_FSR_PGERR   ((uint8_t)0x10)
#define	IS25LP064A_FSR_ERERR   ((uint8_t)0x20)
#define	IS25LP064A_FSR_ERSUS   ((uint8_t)0x40)
#define	IS25LP064A_FSR_READY    ((uint8_t)0x80)
#define	ENTER_DEEP_POWER_DOWN   0XB9
#define	EXIT_DEEP_POWER_DOWN   0XB9
#define	RESET_ENABLE_CMD   0x66
#define	RESET_MEMORY_CMD   0x99
#define	READ_ID_CMD   0xAB
#define	READ_ID_CMD2   0x9F
#define	MULTIPLE_IO_READ_ID_CMD   0xAF
#define	READ_SERIAL_FLASH_DISCO_PARAM_CMD   0x5A
#define	READ_MANUFACT_AND_ID   0x90
#define	READ_UNIQUE_ID   0x4B
#define	NO_OP   0x00
#define	SECTOR_UNLOCK   0x26
#define	SECTOR_LOCK   0x24
#define	INFO_ROW_ERASE_CMD   0x64
#define	INFO_ROW_PROGRAM_CMD   0x62
#define	INFO_ROW_READ_CMD   0x68
#define	PAGE_PROG_CMD   0x02
#define	PAGE_PROG_CMD   0x02
#define	QUAD_IN_PAGE_PROG_CMD   0x32
#define	EXT_QUAD_IN_PAGE_PROG_CMD   0x38
#define	READ_CMD   0x03
#define	FAST_READ_CMD   0x0B
#define	FAST_READ_DTR_CMD   0x0D
#define	DUAL_OUT_FAST_READ_CMD   0x3B
#define	DUAL_INOUT_FAST_READ_CMD   0xBB
#define	DUAL_INOUT_FAST_READ_DTR_CMD   0xBD
#define	QUAD_OUT_FAST_READ_CMD   0x6B
#define	QUAD_INOUT_FAST_READ_CMD   0xEB
#define	QUAD_INOUT_FAST_READ_DTR_CMD   0xED
#define	WRITE_ENABLE_CMD   0x06
#define	WRITE_DISABLE_CMD   0x04
#define	READ_STATUS_REG_CMD   0x05
#define	WRITE_STATUS_REG_CMD   0x01
#define	READ_FUNCTION_REGISTER   0X48
#define	WRITE_FUNCTION_REGISTER   0x42
#define	READ_READ_PARAM_REG_CMD   0x61
#define	READ_EXT_READ_PARAM_CMD   0x81
#define	CLEAR_EXT_READ_PARAM_CMD   0x82
#define	WRITE_READ_PARAM_REG_CMD   0xC0
#define	WRITE_NV_READ_PARAM_REG_CMD   0x65
#define	EXT_WRITE_READ_PARAM_REG_CMD   0x63
#define	WRITE_EXT_READ_PARAM_REG_CMD   0x83
#define	WRITE_EXT_NV_READ_PARAM_REG_CMD   0x85
#define	QUAD_IN_FAST_PROG_CMD   0x32
#define	EXT_QUAD_IN_FAST_PROG_CMD   0x38
#define	SECTOR_ERASE_CMD   0xd7
#define	SECTOR_ERASE_QPI_CMD   0x20
#define	BLOCK_ERASE_CMD   0xD8
#define	BLOCK_ERASE_32K_CMD   0x52
#define	CHIP_ERASE_CMD   0xC7
#define	EXT_CHIP_ERASE_CMD   0x60
#define	PROG_ERASE_RESUME_CMD   0x7A
#define	EXT_PROG_ERASE_RESUME_CMD   0x30
#define	PROG_ERASE_SUSPEND_CMD   0x75
#define	EXT_PROG_ERASE_SUSPEND_CMD   0xB0
#define	ENTER_QUAD_CMD   0x35
#define	EXIT_QUAD_CMD   0xF5
#define	IS25LP080D_SR_WIP   ((uint8_t)0x01)
	IS25LP08D Registers
#define	IS25LP080D_SR_WREN   ((uint8_t)0x02)
#define	IS25LP080D_SR_SRWREN    ((uint8_t)0x80)
#define	IS25LP080D_SR_QE   ((uint8_t)0x40)
#define	IS25LP080D_NVCR_NBADDR    ((uint16_t)0x0001)
#define	IS25LP080D_NVCR_SEGMENT    ((uint16_t)0x0002)
#define	IS25LP080D_NVCR_DUAL   ((uint16_t)0x0004)
#define	IS25LP080D_NVCR_QUAB   ((uint16_t)0x0008)
#define	IS25LP080D_NVCR_RH   ((uint16_t)0x0010)
#define	IS25LP080D_NVCR_DTRP    ((uint16_t)0x0020)
#define	IS25LP080D_NVCR_ODS   ((uint16_t)0x01C0)
#define	IS25LP080D_NVCR_XIP    ((uint16_t)0x0E00)
#define	IS25LP080D_NVCR_NB_DUMMY    ((uint16_t)0xF000)
#define	IS25LP080D_VCR_WRAP   ((uint8_t)0x03)
#define	IS25LP080D_VCR_XIP   ((uint8_t)0x08)
#define	IS25LP080D_VCR_NB_DUMMY    ((uint8_t)0xF0)
#define	IS25LP080D_EAR_HIGHEST_SE    ((uint8_t)0x03)
#define	IS25LP080D_EAR_THIRD_SEG    ((uint8_t)0x02)
#define	IS25LP080D_EAR_SECOND_SEG    ((uint8_t)0x01)
#define	IS25LP080D_EAR_LOWEST_SEG    ((uint8_t)0x00)
#define	IS25LP080D_EVCR_ODS   ((uint8_t)0x07)
#define	IS25LP080D_EVCR_RH   ((uint8_t)0x10)
#define	IS25LP080D_EVCR_DTRP    ((uint8_t)0x20)
#define	IS25LP080D_EVCR_DUAL   ((uint8_t)0x40)
#define	IS25LP080D_EVCR_QUAD   ((uint8_t)0x80)
#define	IS25LP080D_FSR_NBADDR    ((uint8_t)0x01)
#define	IS25LP080D_FSR_PRERR   ((uint8_t)0x02)
#define	IS25LP080D_FSR_PGSUS   ((uint8_t)0x04)
#define	IS25LP080D_FSR_PGERR   ((uint8_t)0x10)
#define	IS25LP080D_FSR_ERERR   ((uint8_t)0x20)
#define	IS25LP080D_FSR_ERSUS   ((uint8_t)0x40)
#define	IS25LP080D_FSR_READY    ((uint8_t)0x80)

Macro Definition Documentation

BLOCK_ERASE_32K_CMD [1/2]

#define BLOCK_ERASE_32K_CMD   0x52

&

BLOCK_ERASE_32K_CMD [2/2]

#define BLOCK_ERASE_32K_CMD   0x52

&

BLOCK_ERASE_CMD [1/2]

#define BLOCK_ERASE_CMD   0xD8

&

BLOCK_ERASE_CMD [2/2]

#define BLOCK_ERASE_CMD   0xD8

&

CHIP_ERASE_CMD [1/2]

#define CHIP_ERASE_CMD   0xC7

&

CHIP_ERASE_CMD [2/2]

#define CHIP_ERASE_CMD   0xC7

&

CLEAR_EXT_READ_PARAM_CMD

#define CLEAR_EXT_READ_PARAM_CMD   0x82

&

DUAL_INOUT_FAST_READ_CMD [1/2]

#define DUAL_INOUT_FAST_READ_CMD   0xBB

&

DUAL_INOUT_FAST_READ_CMD [2/2]

#define DUAL_INOUT_FAST_READ_CMD   0xBB

&

DUAL_INOUT_FAST_READ_DTR_CMD [1/2]

#define DUAL_INOUT_FAST_READ_DTR_CMD   0xBD

&

DUAL_INOUT_FAST_READ_DTR_CMD [2/2]

#define DUAL_INOUT_FAST_READ_DTR_CMD   0xBD

&

DUAL_OUT_FAST_READ_CMD [1/2]

#define DUAL_OUT_FAST_READ_CMD   0x3B

&

DUAL_OUT_FAST_READ_CMD [2/2]

#define DUAL_OUT_FAST_READ_CMD   0x3B

&

ENTER_DEEP_POWER_DOWN [1/2]

#define ENTER_DEEP_POWER_DOWN   0XB9

Low Power Modes &

ENTER_DEEP_POWER_DOWN [2/2]

#define ENTER_DEEP_POWER_DOWN   0XB9

Low Power Modes &

ENTER_QUAD_CMD [1/2]

#define ENTER_QUAD_CMD   0x35

Quad Operations

ENTER_QUAD_CMD [2/2]

#define ENTER_QUAD_CMD   0x35

Quad Operations

EXIT_DEEP_POWER_DOWN [1/2]

#define EXIT_DEEP_POWER_DOWN   0XB9

&

EXIT_DEEP_POWER_DOWN [2/2]

#define EXIT_DEEP_POWER_DOWN   0XB9

&

EXIT_QUAD_CMD [1/2]

#define EXIT_QUAD_CMD   0xF5

&

EXIT_QUAD_CMD [2/2]

#define EXIT_QUAD_CMD   0xF5

&

EXT_CHIP_ERASE_CMD [1/2]

#define EXT_CHIP_ERASE_CMD   0x60

&

EXT_CHIP_ERASE_CMD [2/2]

#define EXT_CHIP_ERASE_CMD   0x60

&

EXT_PROG_ERASE_RESUME_CMD [1/2]

#define EXT_PROG_ERASE_RESUME_CMD   0x30

&

EXT_PROG_ERASE_RESUME_CMD [2/2]

#define EXT_PROG_ERASE_RESUME_CMD   0x30

&

EXT_PROG_ERASE_SUSPEND_CMD [1/2]

#define EXT_PROG_ERASE_SUSPEND_CMD   0xB0

&

EXT_PROG_ERASE_SUSPEND_CMD [2/2]

#define EXT_PROG_ERASE_SUSPEND_CMD   0xB0

&

EXT_QUAD_IN_FAST_PROG_CMD

#define EXT_QUAD_IN_FAST_PROG_CMD   0x38

&

EXT_QUAD_IN_PAGE_PROG_CMD [1/2]

#define EXT_QUAD_IN_PAGE_PROG_CMD   0x38

&

EXT_QUAD_IN_PAGE_PROG_CMD [2/2]

#define EXT_QUAD_IN_PAGE_PROG_CMD   0x38

&

EXT_WRITE_READ_PARAM_REG_CMD

#define EXT_WRITE_READ_PARAM_REG_CMD   0x63

volatile

FAST_READ_CMD [1/2]

#define FAST_READ_CMD   0x0B

&

FAST_READ_CMD [2/2]

#define FAST_READ_CMD   0x0B

&

FAST_READ_DTR_CMD [1/2]

#define FAST_READ_DTR_CMD   0x0D

&

FAST_READ_DTR_CMD [2/2]

#define FAST_READ_DTR_CMD   0x0D

&

INFO_ROW_ERASE_CMD [1/2]

#define INFO_ROW_ERASE_CMD   0x64

Security Information Row &

INFO_ROW_ERASE_CMD [2/2]

#define INFO_ROW_ERASE_CMD   0x64

Security Information Row &

INFO_ROW_PROGRAM_CMD [1/2]

#define INFO_ROW_PROGRAM_CMD   0x62

&

INFO_ROW_PROGRAM_CMD [2/2]

#define INFO_ROW_PROGRAM_CMD   0x62

&

INFO_ROW_READ_CMD [1/2]

#define INFO_ROW_READ_CMD   0x68

&

INFO_ROW_READ_CMD [2/2]

#define INFO_ROW_READ_CMD   0x68

&

IS25LP064A_EAR_HIGHEST_SE

#define IS25LP064A_EAR_HIGHEST_SE    ((uint8_t)0x03)

Select the Highest 128Mb segment

IS25LP064A_EAR_LOWEST_SEG

#define IS25LP064A_EAR_LOWEST_SEG    ((uint8_t)0x00)

Select the Lowest 128Mb segment (default)

IS25LP064A_EAR_SECOND_SEG

#define IS25LP064A_EAR_SECOND_SEG    ((uint8_t)0x01)

Select the Second 128Mb segment

IS25LP064A_EAR_THIRD_SEG

#define IS25LP064A_EAR_THIRD_SEG    ((uint8_t)0x02)

Select the Third 128Mb segment

IS25LP064A_EVCR_DTRP

#define IS25LP064A_EVCR_DTRP    ((uint8_t)0x20)

Double transfer rate protocol

IS25LP064A_EVCR_DUAL

#define IS25LP064A_EVCR_DUAL   ((uint8_t)0x40)

Dual I/O protocol

IS25LP064A_EVCR_ODS

#define IS25LP064A_EVCR_ODS   ((uint8_t)0x07)

Output driver strength

IS25LP064A_EVCR_QUAD

#define IS25LP064A_EVCR_QUAD   ((uint8_t)0x80)

Quad I/O protocol

IS25LP064A_EVCR_RH

#define IS25LP064A_EVCR_RH   ((uint8_t)0x10)

Reset/hold

IS25LP064A_FSR_ERERR

#define IS25LP064A_FSR_ERERR   ((uint8_t)0x20)

Erase error

IS25LP064A_FSR_ERSUS

#define IS25LP064A_FSR_ERSUS   ((uint8_t)0x40)

Erase operation suspended

IS25LP064A_FSR_NBADDR

#define IS25LP064A_FSR_NBADDR    ((uint8_t)0x01)

3-bytes or 4-bytes addressing

IS25LP064A_FSR_PGERR

#define IS25LP064A_FSR_PGERR   ((uint8_t)0x10)

Program error

IS25LP064A_FSR_PGSUS

#define IS25LP064A_FSR_PGSUS   ((uint8_t)0x04)

Program operation suspended

IS25LP064A_FSR_PRERR

#define IS25LP064A_FSR_PRERR   ((uint8_t)0x02)

Protection error

IS25LP064A_FSR_READY

#define IS25LP064A_FSR_READY    ((uint8_t)0x80)

Ready or command in progress

IS25LP064A_NVCR_DTRP

#define IS25LP064A_NVCR_DTRP    ((uint16_t)0x0020)

Double transfer rate protocol

IS25LP064A_NVCR_DUAL

#define IS25LP064A_NVCR_DUAL   ((uint16_t)0x0004)

Dual I/O protocol

IS25LP064A_NVCR_NB_DUMMY

#define IS25LP064A_NVCR_NB_DUMMY    ((uint16_t)0xF000)

Number of dummy clock cycles

IS25LP064A_NVCR_NBADDR

#define IS25LP064A_NVCR_NBADDR    ((uint16_t)0x0001)

3-bytes or 4-bytes addressing

IS25LP064A_NVCR_ODS

#define IS25LP064A_NVCR_ODS   ((uint16_t)0x01C0)

Output driver strength

IS25LP064A_NVCR_QUAB

#define IS25LP064A_NVCR_QUAB   ((uint16_t)0x0008)

Quad I/O protocol

IS25LP064A_NVCR_RH

#define IS25LP064A_NVCR_RH   ((uint16_t)0x0010)

Reset/hold

IS25LP064A_NVCR_SEGMENT

#define IS25LP064A_NVCR_SEGMENT    ((uint16_t)0x0002)

Upper or lower 128Mb segment selected by default

IS25LP064A_NVCR_XIP

#define IS25LP064A_NVCR_XIP    ((uint16_t)0x0E00)

XIP mode at power-on reset

IS25LP064A_SR_QE

#define IS25LP064A_SR_QE   ((uint8_t)0x40)

&

IS25LP064A_SR_SRWREN

#define IS25LP064A_SR_SRWREN    ((uint8_t)0x80)

Status register write enable/disable

IS25LP064A_SR_WIP

#define IS25LP064A_SR_WIP   ((uint8_t)0x01)

IS25LP08D Registers

Write in progress

IS25LP064A_SR_WREN

#define IS25LP064A_SR_WREN   ((uint8_t)0x02)

Write enable latch

IS25LP064A_VCR_NB_DUMMY

#define IS25LP064A_VCR_NB_DUMMY    ((uint8_t)0xF0)

Number of dummy clock cycles

IS25LP064A_VCR_WRAP

#define IS25LP064A_VCR_WRAP   ((uint8_t)0x03)

Wrap

IS25LP064A_VCR_XIP

#define IS25LP064A_VCR_XIP   ((uint8_t)0x08)

XIP

IS25LP080D_EAR_HIGHEST_SE

#define IS25LP080D_EAR_HIGHEST_SE    ((uint8_t)0x03)

Select the Highest 128Mb segment

IS25LP080D_EAR_LOWEST_SEG

#define IS25LP080D_EAR_LOWEST_SEG    ((uint8_t)0x00)

Select the Lowest 128Mb segment (default)

IS25LP080D_EAR_SECOND_SEG

#define IS25LP080D_EAR_SECOND_SEG    ((uint8_t)0x01)

Select the Second 128Mb segment

IS25LP080D_EAR_THIRD_SEG

#define IS25LP080D_EAR_THIRD_SEG    ((uint8_t)0x02)

Select the Third 128Mb segment

IS25LP080D_EVCR_DTRP

#define IS25LP080D_EVCR_DTRP    ((uint8_t)0x20)

Double transfer rate protocol

IS25LP080D_EVCR_DUAL

#define IS25LP080D_EVCR_DUAL   ((uint8_t)0x40)

Dual I/O protocol

IS25LP080D_EVCR_ODS

#define IS25LP080D_EVCR_ODS   ((uint8_t)0x07)

Output driver strength

IS25LP080D_EVCR_QUAD

#define IS25LP080D_EVCR_QUAD   ((uint8_t)0x80)

Quad I/O protocol

IS25LP080D_EVCR_RH

#define IS25LP080D_EVCR_RH   ((uint8_t)0x10)

Reset/hold

IS25LP080D_FSR_ERERR

#define IS25LP080D_FSR_ERERR   ((uint8_t)0x20)

Erase error

IS25LP080D_FSR_ERSUS

#define IS25LP080D_FSR_ERSUS   ((uint8_t)0x40)

Erase operation suspended

IS25LP080D_FSR_NBADDR

#define IS25LP080D_FSR_NBADDR    ((uint8_t)0x01)

3-bytes or 4-bytes addressing

IS25LP080D_FSR_PGERR

#define IS25LP080D_FSR_PGERR   ((uint8_t)0x10)

Program error

IS25LP080D_FSR_PGSUS

#define IS25LP080D_FSR_PGSUS   ((uint8_t)0x04)

Program operation suspended

IS25LP080D_FSR_PRERR

#define IS25LP080D_FSR_PRERR   ((uint8_t)0x02)

Protection error

IS25LP080D_FSR_READY

#define IS25LP080D_FSR_READY    ((uint8_t)0x80)

Ready or command in progress

IS25LP080D_NVCR_DTRP

#define IS25LP080D_NVCR_DTRP    ((uint16_t)0x0020)

Double transfer rate protocol

IS25LP080D_NVCR_DUAL

#define IS25LP080D_NVCR_DUAL   ((uint16_t)0x0004)

Dual I/O protocol

IS25LP080D_NVCR_NB_DUMMY

#define IS25LP080D_NVCR_NB_DUMMY    ((uint16_t)0xF000)

Number of dummy clock cycles

IS25LP080D_NVCR_NBADDR

#define IS25LP080D_NVCR_NBADDR    ((uint16_t)0x0001)

3-bytes or 4-bytes addressing

IS25LP080D_NVCR_ODS

#define IS25LP080D_NVCR_ODS   ((uint16_t)0x01C0)

Output driver strength

IS25LP080D_NVCR_QUAB

#define IS25LP080D_NVCR_QUAB   ((uint16_t)0x0008)

Quad I/O protocol

IS25LP080D_NVCR_RH

#define IS25LP080D_NVCR_RH   ((uint16_t)0x0010)

Reset/hold

IS25LP080D_NVCR_SEGMENT

#define IS25LP080D_NVCR_SEGMENT    ((uint16_t)0x0002)

Upper or lower 128Mb segment selected by default

IS25LP080D_NVCR_XIP

#define IS25LP080D_NVCR_XIP    ((uint16_t)0x0E00)

XIP mode at power-on reset

IS25LP080D_SR_QE

#define IS25LP080D_SR_QE   ((uint8_t)0x40)

&

IS25LP080D_SR_SRWREN

#define IS25LP080D_SR_SRWREN    ((uint8_t)0x80)

Status register write enable/disable

IS25LP080D_SR_WIP

#define IS25LP080D_SR_WIP   ((uint8_t)0x01)

IS25LP08D Registers

Status Register Write in progress

IS25LP080D_SR_WREN

#define IS25LP080D_SR_WREN   ((uint8_t)0x02)

Write enable latch

IS25LP080D_VCR_NB_DUMMY

#define IS25LP080D_VCR_NB_DUMMY    ((uint8_t)0xF0)

Number of dummy clock cycles

IS25LP080D_VCR_WRAP

#define IS25LP080D_VCR_WRAP   ((uint8_t)0x03)

Wrap

IS25LP080D_VCR_XIP

#define IS25LP080D_VCR_XIP   ((uint8_t)0x08)

XIP

MULTIPLE_IO_READ_ID_CMD [1/2]

#define MULTIPLE_IO_READ_ID_CMD   0xAF

&

MULTIPLE_IO_READ_ID_CMD [2/2]

#define MULTIPLE_IO_READ_ID_CMD   0xAF

&

NO_OP [1/2]

#define NO_OP   0x00

Cancels Reset Enable

NO_OP [2/2]

#define NO_OP   0x00

Cancels Reset Enable

PAGE_PROG_CMD [1/3]

#define PAGE_PROG_CMD   0x02

Page Program Operations

Page Operations

Program Operations

PAGE_PROG_CMD [2/3]

#define PAGE_PROG_CMD   0x02

Page Operations

Program Operations

PAGE_PROG_CMD [3/3]

#define PAGE_PROG_CMD   0x02

Page Operations

Program Operations

PROG_ERASE_RESUME_CMD [1/2]

#define PROG_ERASE_RESUME_CMD   0x7A

&

PROG_ERASE_RESUME_CMD [2/2]

#define PROG_ERASE_RESUME_CMD   0x7A

&

PROG_ERASE_SUSPEND_CMD [1/2]

#define PROG_ERASE_SUSPEND_CMD   0x75

&

PROG_ERASE_SUSPEND_CMD [2/2]

#define PROG_ERASE_SUSPEND_CMD   0x75

&

QUAD_IN_FAST_PROG_CMD

#define QUAD_IN_FAST_PROG_CMD   0x32

&

QUAD_IN_PAGE_PROG_CMD [1/2]

#define QUAD_IN_PAGE_PROG_CMD   0x32

&

QUAD_IN_PAGE_PROG_CMD [2/2]

#define QUAD_IN_PAGE_PROG_CMD   0x32

&

QUAD_INOUT_FAST_READ_CMD [1/2]

#define QUAD_INOUT_FAST_READ_CMD   0xEB

&

QUAD_INOUT_FAST_READ_CMD [2/2]

#define QUAD_INOUT_FAST_READ_CMD   0xEB

&

QUAD_INOUT_FAST_READ_DTR_CMD [1/2]

#define QUAD_INOUT_FAST_READ_DTR_CMD   0xED

&

QUAD_INOUT_FAST_READ_DTR_CMD [2/2]

#define QUAD_INOUT_FAST_READ_DTR_CMD   0xED

&

QUAD_OUT_FAST_READ_CMD [1/2]

#define QUAD_OUT_FAST_READ_CMD   0x6B

&

QUAD_OUT_FAST_READ_CMD [2/2]

#define QUAD_OUT_FAST_READ_CMD   0x6B

&

READ_CMD [1/2]

#define READ_CMD   0x03

Read Operations

READ_CMD [2/2]

#define READ_CMD   0x03

Read Operations

READ_EXT_READ_PARAM_CMD

#define READ_EXT_READ_PARAM_CMD   0x81

&

READ_FUNCTION_REGISTER [1/2]

#define READ_FUNCTION_REGISTER   0X48

&

READ_FUNCTION_REGISTER [2/2]

#define READ_FUNCTION_REGISTER   0X48

&

READ_ID_CMD [1/2]

#define READ_ID_CMD   0xAB

Identification Operations

READ_ID_CMD [2/2]

#define READ_ID_CMD   0xAB

Identification Operations

READ_ID_CMD2 [1/2]

#define READ_ID_CMD2   0x9F

&

READ_ID_CMD2 [2/2]

#define READ_ID_CMD2   0x9F

&

READ_MANUFACT_AND_ID [1/2]

#define READ_MANUFACT_AND_ID   0x90

&

READ_MANUFACT_AND_ID [2/2]

#define READ_MANUFACT_AND_ID   0x90

&

READ_READ_PARAM_REG_CMD

#define READ_READ_PARAM_REG_CMD   0x61

&

READ_SERIAL_FLASH_DISCO_PARAM_CMD [1/2]

#define READ_SERIAL_FLASH_DISCO_PARAM_CMD   0x5A

&

READ_SERIAL_FLASH_DISCO_PARAM_CMD [2/2]

#define READ_SERIAL_FLASH_DISCO_PARAM_CMD   0x5A

&

READ_STATUS_REG_CMD [1/2]

#define READ_STATUS_REG_CMD   0x05

Register Operations

READ_STATUS_REG_CMD [2/2]

#define READ_STATUS_REG_CMD   0x05

Register Operations

READ_UNIQUE_ID [1/2]

#define READ_UNIQUE_ID   0x4B

&

READ_UNIQUE_ID [2/2]

#define READ_UNIQUE_ID   0x4B

&

RESET_ENABLE_CMD [1/2]

#define RESET_ENABLE_CMD   0x66

Reset Operations

RESET_ENABLE_CMD [2/2]

#define RESET_ENABLE_CMD   0x66

Reset Operations

RESET_MEMORY_CMD [1/2]

#define RESET_MEMORY_CMD   0x99

&

RESET_MEMORY_CMD [2/2]

#define RESET_MEMORY_CMD   0x99

&

SECTOR_ERASE_CMD [1/2]

#define SECTOR_ERASE_CMD   0xd7

Erase Operations

SECTOR_ERASE_CMD [2/2]

#define SECTOR_ERASE_CMD   0xd7

Erase Operations

SECTOR_ERASE_QPI_CMD [1/2]

#define SECTOR_ERASE_QPI_CMD   0x20

&

SECTOR_ERASE_QPI_CMD [2/2]

#define SECTOR_ERASE_QPI_CMD   0x20

&

SECTOR_LOCK [1/2]

#define SECTOR_LOCK   0x24

&

SECTOR_LOCK [2/2]

#define SECTOR_LOCK   0x24

&

SECTOR_UNLOCK [1/2]

#define SECTOR_UNLOCK   0x26

&

SECTOR_UNLOCK [2/2]

#define SECTOR_UNLOCK   0x26

&

WRITE_DISABLE_CMD [1/2]

#define WRITE_DISABLE_CMD   0x04

&

WRITE_DISABLE_CMD [2/2]

#define WRITE_DISABLE_CMD   0x04

&

WRITE_ENABLE_CMD [1/2]

#define WRITE_ENABLE_CMD   0x06

Write Operations

WRITE_ENABLE_CMD [2/2]

#define WRITE_ENABLE_CMD   0x06

Write Operations

WRITE_EXT_NV_READ_PARAM_REG_CMD

#define WRITE_EXT_NV_READ_PARAM_REG_CMD   0x85

non-volatile

WRITE_EXT_READ_PARAM_REG_CMD

#define WRITE_EXT_READ_PARAM_REG_CMD   0x83

volatile

WRITE_FUNCTION_REGISTER [1/2]

#define WRITE_FUNCTION_REGISTER   0x42

&

WRITE_FUNCTION_REGISTER [2/2]

#define WRITE_FUNCTION_REGISTER   0x42

&

WRITE_NV_READ_PARAM_REG_CMD

#define WRITE_NV_READ_PARAM_REG_CMD   0x65

non-volatile

WRITE_READ_PARAM_REG_CMD [1/2]

#define WRITE_READ_PARAM_REG_CMD   0xC0

&

volatile

WRITE_READ_PARAM_REG_CMD [2/2]

#define WRITE_READ_PARAM_REG_CMD   0xC0

volatile

WRITE_STATUS_REG_CMD [1/2]

#define WRITE_STATUS_REG_CMD   0x01

&

WRITE_STATUS_REG_CMD [2/2]

#define WRITE_STATUS_REG_CMD   0x01

&